The present invention relates generally to silicon-on-insulator devices and in particular the present invention relates to fully depleted silicon-on-insulator logic.
The increased speed and capability of computers and other electronic devices requires better performance from the integrated circuits that make up a device. One way to make the integrated circuits faster is to reduce the size of the transistors that make up the device. However, as transistors are made smaller and faster, delays through the connections between the transistors becomes greater in relation to the speed of the transistor.
An alternative technique to speed up integrated circuits is to use alternative semiconductors. For example, silicon-on-insulator (SOI) technology provides a 25-35% performance increase over equivalent CMOS technologies. SOI refers to placing a thin layer of silicon on top of an insulator such as silicon oxide or glass. The transistors would then be built on this thin layer of SOI. The SOI layer reduces the capacitance of the transistors so that they operate faster.
FIG. 1 illustrates a typical SOI semiconductor. The transistor is formed in the silicon layer 101 that is over the insulator 102. The insulator is formed on top of the substrate 103. Within the silicon layer 101, the drain/source regions 105 and 106 are formed. The gate 107 is formed above the partially depleted channel 109. A floating body 110 is within the depleted region 112 and results from the partial depletion.
SOI technology, however, imposes significant technical challenges. The silicon film used for SOI transistors must be perfect crystalline silicon. The insulator layer, however, is not crystalline. It is very difficult to make perfect crystalline silicon-on-oxide or silicon with other insulators since the insulator layer""s crystalline properties are so different from the pure silicon. If perfect crystalline silicon is not obtained, defects will find their way onto the SOI film. This degrades the transistor performance.
Additionally, if the p-type body is contacted by implanted regions there will be a very high resistance of the body region, particularly if the transistor is wide. Impact ionization can cause a large current through this resistance and forward bias the body, thus resulting in transients.
One alternative to this floating body effect is the fully depleted silicon-on-sapphire (SOS) semiconductor. This type of semiconductor does not have a partially depleted silicon layer or floating body. However, they can still experience a problem where the drain current does not stay constant as the drain voltage increases when the transistor is in the saturation region of operation. Instead, the current xe2x80x9ckinksxe2x80x9d up to a higher value. Clearly, the collection of carriers either on a floating body or near the source is undesirable.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to control adverse floating body effects in partially depleted CMOS devices using SOI technology.
The above-mentioned problems with adverse floating body effects and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
The present invention encompasses a method for generating a fully depleted body structure in a silicon-on-insulator device. The method provides an extractor contact coupled to the body structure. An extractor voltage is provided such that the extractor contact is reverse biased and minority carriers in the body structure are removed.
Further embodiments of the invention include methods and apparatus of varying scope.